Mohammed Thouqeer
RTL Design Engineer
Verified
MT
Over 2 years of experience as a RTL Design Engineer, focused on developing micro-architecture, RTL coding, Lint, CDC and Synthesis.
Subjects
Verilog
Linux commands
gvim commands
SystemVerilog
Basic projects using Verilog
Real time project RISC-V Processor
Experience
2+ years teaching experience
Education
No education information provided.
Fee details
$12.5–25/hour (USD)
Reviews
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Location
Bengaluru
Teaches online
Yes
Teaches at student's home
No
Total Teaching exp
2+ yrs.
Gender
Male
Speaks
English, Hindi, Kannada
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